The present invention relates to electron beam exposure, and more particularly to that for drawing such a pattern as an IC (Integrated Circuit) directly on a semiconductor wafer.
Micro-miniaturization and high density integration of semiconductor IC chips have been remarkably progressed in recent years, and ultra-fine design rules are applied now.
Formerly, optical exposure is used for pattern printing in most mass-production lines of IC chips. However, a spotlight is now on the electron beam exposure, which has high resolution and needs no reticle, for processing the ultra-fine pattern difficult to be printed with the optical exposure. In order to male use of the high productivity of the optical exposure as well as the high resolution of the electron beam exposure, a hybrid technology is pursued to apply the optical exposure to patterns having larger design rules and the electron beam exposure to those having ultra-fine design rules.
FIG. 4 is a schematic diagram illustrating configuration of a conventional example of the electron beam exposure system.
The apparatus of FIG. 4 has a main body 1 comprising an electron gun 11 for generating an electron beam 10 which is accelerated with an electric field impressed by an acceleration supply 16, an electron barrel 12 including various electrodes such as electromagnetic lenses and apertures taking charge of control of the electron beam 10, that is, converging, blanking, positioning or intensity control thereof, for example, and a material chamber 13 including a wafer table whereon a wafer 20 is placed for drawing, and an X-Y stage 15 for controlling position of the wafer table. The main body 1 are sucked into vacuum by vacuum pumps 4A to 4C and installed on an anti-vibration table 5.
A computer 3B is provided for controlling the X-Y stage 15 and the electron beam 10 through the electrodes of the barrel 12 to expose a pattern on the wafer 20 according to pattern data supplied from a data storage 2B, making use of preset drawing parameters.
In the following paragraphs, field dividing and superimpose procedure of the hybrid technology according to the conventional system of FIG. 4 is described.
When biasing angle of the electron beam becomes larger than a limit, biasing distortion becomes not negligible degrading the drawing precision, in the electron beam exposure. Therefore, there is a limitation of the drawing area, which is called a field, where the electron beam can be shifted for pattern drawing within negligible biasing distortion. The size of the field is, generally, smaller than a desired chip size, and so, the electron beam exposure of a chip pattern is performed field by field, dividing the chip pattern into a plurality of fields each having a certain size.
As for the field dividing procedure, a method is disclosed in a Japanese patent application laid open as a Provisional Publication No. 219617/'91, wherein drawing data are divided into data of a plurality of sub fields, length of a side thereof being 1/N of a side of a maximum allowable field of the apparatus, N being a positive integer more than one. When high resolution is required, the electron beam exposure is performed each by each of the sub fields in the prior art, while it is performed on several sub fields not more than N.times.N sub fields, namely, the maximum allowable field, at once, where comparatively low resolution is allowed.
Another method is disclosed in a Japanese Patent Publication No. 15139/'96, wherein a small field size is applied for drawing a small pattern with sufficient preciseness and a large field size is applied for drawing a large pattern for maintaining throughput performance.
Now the superimpose procedure in the hybrid technology is described in connection with prior examples disclosed in Japanese patent applications laid open as Provisional Publications No. 186331/'82 and No. 057216/'87.
In the prior art of the Provisional Publication No. 186331/'82, reference marks for distortion measuring are provided on a reticle used for the optical exposure. By detecting the reference marks printed on a wafer, distortion amount of the printed pattern is measured by the electron beam exposure system, which is added to a positioning signal of the electron beam for superimposing fine patterns. Thus, a hybrid exposure is performed in this prior art.
In the prior art of the Provisional Publication No. 057216/'87, a compensation signal is prepared from distortion values beforehand measured of the optical exposure system according to kind of the pattern to be superimposed, that is, according to difference between a reticle pattern and a mask pattern.
However, in the hybrid technology wherein new patterns are superimposed by the electron beam exposure on a first pattern already printed by the optical exposure, the biasing distortion, previously mentioned, of the electron beam is derived in each field in addition to the optical distortion of the first pattern which is spread over its chip size. Furthermore, amount and variation, or differential of the optical distortion depend on position of each field relative to the chip size. Therefore, when design rule dimension become ultra-fine, it becomes very difficult to superimpose the electron beam pattern on the first pattern printed by the optical exposure with sufficient preciseness and sufficient efficiency, according to the hybrid technology of the prior arts wherein the size of the sub field or the small field is predetermined uniformly, even when the optical distortion can be measured exactly.